Integrated circuits are widely used in electronic devices, such as computers, cellular telephones, entertainment systems, etc. A typical integrated circuit includes a semiconductor substrate with a plurality of active regions formed therein. These active regions may be interconnected by various conductive or metal lines formed in layers on the substrate. Accordingly, an integrated circuit may include millions of transistors, for example.
As the densities of integrated circuits are continually increased, each feature, such as the width of a metal line, or the width of a polygate oxide layer, is continually reduced. Smaller features permit faster operation, less power consumption and more complicated functions to be performed. Such features are typically defined by selective exposure of a photoresist layer on a semiconductor wafer to a pattern imaged from a mask or reticle in a process generally known as optical lithography or photolithography. The exposed photoresist layer portions may be made etch resistant upon exposure to the image, for example. The non-exposed portions may then be removed leaving the desired photoresist pattern. The chemistry of the photoresist may also provide that exposed portions are etched and non-exposed portions remain. The remaining resist portions are then typically used to provide selective etching of the underlying integrated circuit portions.
The resolution and hence minimum feature size is related to the wavelength of light used in the photolithography. The so-called Rayleigh resolution criteria will soon define the limit of physics for imaging the ever-shrinking feature size in integrated circuit manufacturing. Continuing developments have allowed optical lithography to keep pace with decreasing feature sizes. As noted in the IEEE Spectrum article "Ultralight lithography" appearing at pp. 35-40, in July 1999, the lifetime of a given lithography generation is modified until a complete change to a next generation technology is made. In other words, various corrective measures are taken to help pattern smaller features, and which is limited by the wavelength of light used. Typical corrective techniques include optical proximity correction (OPC) and the use of phase-shift masks. Unfortunately, such phase-shift masks and OPC masks can be relatively expensive.
One possible alternative is to use successive printing or exposure steps, wherein a shift is performed between successive exposures as disclosed in U.S. Pat. Nos. 5,905,020 to Hu et al. and 5,811,222 to Gardner et al., for example. The Hu et al. patent in particular recognizes that to achieve a precise critical dimension, it was necessary to adjust the magnitude of the positional shift to account for process factors, such as the contrast of the photoresist and the degree of photoresist swelling during development. This compensation factor for a given process is described as being empirically determined based upon the critical dimension sought. In most cases this compensation factor fell within a range of 0.8 to 1.8.
Unfortunately, as circuit feature sizes are yet further reduced the overlap printing approach is useful, but may produce inaccurate features. This is so because only a constant scalar compensation factor is used. In many applications, the constant scalar compensation factor produces unacceptable results.